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TS274
High performance CMOS quad ooperational amplifiers

Output voltage can swing to ground Excellent phase margin on capacitive loads Gain bandwidth product: 3.5MHz Stable and low offset voltage Three input offset voltage selections N DIP-14 (Plastic Package)
Description
The TS274 devices are low cost, quad operational amplifiers designed to operate with single or dual supplies. These operational amplifiers use the ST silicon gate CMOS process allowing an excellent consumption-speed ration. These series are ideally suited for low consumption applications. Three power consumptions are available allowing to have always the best consumption-speed ratio: - ICC = 10A/amp.: TS27L4 (very low power) - ICC = 150A/amp.: TS27M4 (low power) - ICC = 1mA/amp.: TS274 (standard) These CMOS amplifiers offer very high input impedance and extremely low input currents. The major advantage versus JFET devices is the very low input currents drift with temperature (see figure 2).
D SO-14 (Plastic Micropackage)
P TSSOP14 (Thin Shrink Small Outline Package)
Pin connections (top view)
Output 1 1 Inverting Input 1 2 Non-inverting Input 1 3 VCC + 4 Non-inverting Input 2 5 Inverting Input 2 6 Output 2 7 + + + + 14 Output 4 13 Inverting Input 4 12 Non-inverting Input 4 11 VCC 10 Non-inverting Input 3 9 8 Inverting Input 3 Output 3
April 2006
Rev. 2
1/15
www.st.com
15
Order codes
TS274
1
Order codes
Part Number Temperature Range Package Packing Marking 274C 274AC TS274CN TS274ACN
TS274CD/DT TS274ACD/DT TS274CN TS274ACN TS274CPT TS274ACPT TS274ID/DT TS274AID/DT TS274IN TS274AIN TS274IPT TS274AIPT -40C, +125C 0C, +70C
SO-14
Tube or Tape & Reel
DIP 14
Tube
TSSOP 14
Tape & Reel 274I 274AI TS274IN TS274AIN
SO-14
Tube or Tape & Reel
DIP 14
Tube
TSSOP-14
Tape & Reel
2/15
TS274
Absolute maximum ratings & operating conditions
2
Absolute maximum ratings & operating conditions
Table 1.
Symbol VCC+ Vid Vi Io Iin Toper Tstg
Absolute maximum ratings (AMR)
Parameter Supply Voltage (1) Differential Input Voltage Input Voltage (3) Output Current for VCC 15V Input Current Operating Free-Air Temperature Range Storage Temperature Range Thermal Resistance Junction to SO-14 TSSOP14 DIP14 Ambient(4) 103 100 80 31 32 33 500 100 800 C/W 0 to +70
+ (2)
TS274C/AC/BC 18 18
TS274I/AI/BI
Unit V V V mA mA
-0.3 to 18 30 5 -40 to +125
C C
-65 to +150
Rthja
Rthjc
Thermal Resistance Junction to Case SO-14 TSSOP14 DIP14 HBM: Human Body Model(5)
C/W
V V V
ESD
MM: Machine
Model(6)
CDM: Charged Device Model
1. All values, except differential voltage are with respect to network ground terminal. 2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal. 3. The magnitude of the input and the output voltages must never exceed the magnitude of the positive supply voltage. 4. Short-circuits can cause excessive heating and destructive dissipation. Values are typical. 5. Human body model, 100pF discharged through a 1.5k resistor into pin of device. 6. Machine model ESD, a 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (internal resistor < 5), into pin to pin of device.
Table 2.
Symbol VCC
+
Operating conditions
Parameter Supply Voltage Common Mode Input Voltage Range Value 3 to 16 0 to VCC+ - 1.5 Unit V V
Vicm
3/15
Typical application information
TS274
3
Typical application information
Figure 1. Block diagram
VCC
Current source
xI
Input differential
Second stage
Output stage
Output
VCC
E E
4/15
TS274 Figure 2.
VCC
T24
T 25
T 26 T6 T8
T27 T5
T 10 T 15
R2 T28 T1
Input
T 18
T2
Input R1 C1
T11
T 12
Schematic diagram (for 1/4 TS274)
T17
T7
T 23 T3
Output
T19 T4
T16
T9 T 13 T 14
T20
T 22
T21
T29
Typical application information
VCC
5/15
Electrical characteristics
TS274
4
Electrical characteristics
Table 3. VCC+ = +10V, VCC-= 0V, Tamb = +25C (unless otherwise specified)
TS274C/AC/BC TS274I/AI/BI Unit Min VO = 1.4V, Vic = 0V TS274C/I TS274AC/AI TS274B/C/I Vio Input Offset Voltage Tmin Tamb T max TS274C/I TS274AC/AI TS274B/C/I 2 Vic = 5V, VO = 5V Tmin Tamb T max Vic = 5V, VO = 5V Tmin Tamb T max Vid = 100mV, RL = 10k Tmin Tamb T max Vid = -100mV 10 7 3.5 65 60 80 70 1000 1500 1600 60 45 5.5 40 30 f = 1kHz, R s = 100 30 120 65 60 15 8.2 8.1 1 100 1 150 8.4 50 10 6 3.5 80 70 1000 1500 1700 60 45 5.5 40 30 30 120 MHz dB dB A mA mA V/s Degrees % nV/Hz dB 15 V/mV 8.2 8 8.4 50 1 300 Typ Max Min Typ Max Conditions
Symbol
Parameter
1.1 0.9 0.25
10 5 2 12 6.5 3
1.1 0.9 0.25
10 5 2 mV 12 6.5 3.5
DV io Iio Iib VOH VOL Avd
Input Offset Voltage Drift Input Offset Current (1) Input Bias Current (1) High Level Output Voltage Low Level Output Voltage
2 1 200
V/C pA pA V mV
ViC = 5V, RL = 10k, Large Signal Voltage Gain Vo = 1V to 6V Tmin Tamb T max Gain Bandwidth Product Common Mode Rejection Ratio Supply Voltage Rejection Ratio Supply Current (per amplifier) Output Short Circuit Current Output Sink Current Slew Rate at Unity Gain Phase Margin at Unity Gain Overshoot Factor Equivalent Input Noise Voltage Av = 40dB, RL = 10k, CL = 100pF, fin = 100kHz ViC = 1V to 7.4V, Vo = 1.4V VCC + = 5V to 10V, Vo = 1.4V Av = 1, no load, Vo = 5V Tmin Tamb T max Vo = 0V, Vid = 100mV Vo = VCC, Vid = -100mV RL = 10k, CL = 100pF, Vi = 3 to 7V Av = 40dB, R L = 10k, CL = 100pF
GBP CMR SVR ICC Io Isink SR m KOV en
Vo1 /Vo2 Channel Separation
1. Maximum values including unavoidable inaccuracies of the industrial test.
6/15
TS274 Figure 3. Supply current (each amplifier) vs. supply voltage Figure 4.
Electrical characteristics High level output voltage vs. high level output current
SUPPLY CURRENT, I CC ( A)
1.5 1.0 0.5
Tamb = 25C AV = 1 VO = VCC / 2
OUTPUT VOLTAGE, V OH (V)
2.0
20 16 12 8 4 0 -50 VCC = 10V T amb = 25C V id = 100mV VCC = 16V
0
4 8 12 SUPPLY VOLTAGE, VCC (V)
Input bias current vs. free-air temperature
VCC = 10V Vic = 5V
16
-40 -30 -20 OUTPUT CURRENT, I
-10 OH (mA)
0
Figure 5.
INPUT BIAS CURRENT, I IB (pA) 100
Figure 6.
OUTPUT VOLTAGE, V OL (V)
Low level output voltage vs. low level output current
1.0 0.8 0.6 0.4 0.2 T amb = 25C V ic = 0.5V V id = -100mV 1 2 OUTPUT CURRENT, I OL (mA) 3 V CC = 3V V CC = 5V
10
1 25 50 75 100 125
0
TEMPERATURE, T amb (C)
Figure 7.
OUTPUT VOLTAGE, V OH (V) 5 4 3 2 1 0
High level output voltage vs. high level output current
Figure 8.
OUTPUT VOLTAGE, VOL (V) 3
Low level output voltage vs. low level output current
V CC = 10V VCC = 16V
T amb = 25C V id = 100mV VCC = 5V
2 1
VCC = 3V
T amb = 25C V i = 0.5V V = -100mV
id
-10
-8 -6 -4 -2 OUTPUT CURRENT, I OH (mA)
0
0
4 8 12 16 OUTPUT CURRENT, I OL (mA)
20
7/15
Electrical characteristics Figure 9.
50
P H A S E (D e g re e s )
TS274
Open loop frequency response and Figure 10. Phase margin vs. capacitive load phase shift
P H A S E M A R G IN , m (D e g re e s )
70 Ta m b = 2 5 C R L = 10k AV = 1 VC C = 10V
40 G A IN 30
G A IN (d B )
0 45 Phase Margin 90 135
60
PHASE T a m b = 2 5 C V C C+ = 1 0 V R L = 10k C L = 100pF A VC L = 100 2 3 4
20 10 0 -1 0 10
50 40
Gain Bandwidth Product 10 10 5 10 6 10
180
30 0 20 40 60
L
10
7
80 (p F )
100
F R E Q U E N C Y , f (H z )
C A P A C IT A N C E , C
Figure 11. Gain bandwidth product vs. supply Figure 12. Slew rate vs. supply voltage voltage
G A IN B A N D W . P R O D ., G B P (M H z )
5
7
S L E W R A T E S , S R (V / s )
4 3
6 5 4 3 2
Ta m b = 2 5 C R L = 10k CL = 1 0 0 p F
SR
2 1
Ta m b = 2 5 C R L = 10k CL = 1 0 0 p F AV = 1 4 8 12 16
SR
0
4
S U P P L Y V O L T A G E , V C C (V )
6 8 10 12 S U P P L Y V O L T A G E , VC C
14 (V )
16
Figure 13. Phase margin vs. supply voltage
P H A S E M A R G IN , m (D e g re e s )
Figure 14. Input voltage noise vs. frequency
E Q U IV A L E N T IN P U T N O IS E V O L T A G E (n V /V H z )
300 VC C = 1 0 V Tamb = 2 5 C 200 R S = 1 0 0
48 44 40
36 32 28
Ta m b = 2 5 C R L = 10k CL = 1 0 0 p F AV = 1 0 4 8 12 16
100
0 1 10 100 1000
S U P P L Y V O L T A G E , V C C (V )
F R E Q U E N C Y (H z )
8/15
TS274
Macromodel
5
5.1
Macromodel
Important note concerning this macromodel
Please consider following remarks before using this macromodel. - All models are a trade-off between accuracy and complexity (i.e. simulation time). - Macromodels are not a substitute to breadboarding; rather, they confirm the validity of a design approach and help to select surrounding component values. - A macromodel emulates the NOMINAL performance of a TYPICAL device within SPECIFIED OPERATING CONDITIONS (i.e. temperature, supply voltage, etc.). Thus the macromodel is often not as exhaustive as the datasheet, its goal is to illustrate the main parameters of the product. Data issued from macromodels used outside of its specified conditions (V CC, Temperature, etc.) or even worse: outside of the device operating conditions (VCC, Vicm, etc.) are not reliable in any way.
5.2
Macromodel code
******************************** .SUBCKT TS27X 1 2 3 4 5 *** INP- = 1, INP+ =2, OUT = 3 VDD=4 VSS = 5 *** TYPE = TS271/TS272/TS274 .MODEL MDTH D IS=1E-8 KF=2.664E-16 CJO=10F ***INPUT STAGE CIP 2 5 1E-12 CIN 1 5 1E-12 EIP 10 5 2 5 1 EIN 16 5 1 5 1 RIP 10 11 8 RIN 15 16 8 RIS 11 15 223.84 CPS 11 15 1E-9 DIP 11 120 MDTH 400E-12 DIN 15 140 MDTH 400E-12 RDEG1 12 120 4400 RDEG2 14 140 4400 VOFP 12 13 DC 0 VOFN 13 14 DC 0 IPOL 13 5 38E-6 ***ICC DICC1 4 31 MDTH 400E-12 DICC2 31 32 MDTH 400E-12 DICC3 32 33 MDTH 400E-12 DICC4 33 34 MDTH 400E-12 RICC 34 5 20E3 ICC 4 5 600E-6 ***COMMON MODE INPUT LIMITATION DINN 17 13 MDTH 400E-12 VIN 17 5 DC -0.1 DINR 15 18 MDTH 400E-12 VIP 4 18 DC 2.2 ***GM1 STAGE FGM1P 119 5 VOFP 1 FGM1N 119 5 VOFN 1 RAP 119 4 1E6
9/15
Macromodel RAN 119 5 1E6 ***GM2 STAGE G2P 19 5 119 5 4E-4 G2N 19 5 119 4 4E-4 R2P 19 4 450E3 R2N 19 5 450E3 ***COMPENSATION CC 19 119 7p ***BUFFER EBUF 20 5 19 5 1 ***SHORT-CIRCUIT LIMITATIONS( ISINK, ISOURCE) DOPM 19 22 MDTH 400E-12 DONM 21 19 MDTH 400E-12 HOPM 22 28 VOUT 910 VIPM 28 4 DC 50 HONM 21 27 VOUT 1222 VINM 5 27 DC 50 VOUT 3 23 DC 0 ***VOH, VOL DEFINITIONS DOP 19 25 MDTH 400E-12 VOP 4 25 2.5 DON 24 19 MDTH 400E-12 VON 24 5 0.92 ***OUTPUT RESISTOR ROUT 23 20 10 .ENDS
TS274
10/15
TS274
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
6.1
DIP14 package
Plastic DIP-14 MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 1.27 3.3 2.54 0.050 8.5 2.54 15.24 7.1 5.1 0.130 0.100 0.51 1.39 0.5 0.25 20 0.335 0.100 0.600 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.055 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001A
11/15
Package mechanical data
TS274
6.2
SO-14 package
SO-14 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 8.55 5.8 1.27 7.62 4.0 5.3 1.27 0.68 8 (max.) 0.149 0.181 0.019 8.75 6.2 0.35 0.19 0.5 45 (typ.) 0.336 0.228 0.050 0.300 0.157 0.208 0.050 0.026 0.344 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13G
12/15
TS274
Package mechanical data
6.3
TSSOP14 package
TSSOP14 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0080337D
13/15
Revision history
TS274
7
Revision history
Table 4.
Date Nov. 2001
Document revision history
Revision 1 Initial release. - ESD protection inserted in Table 1. on page 3. - Thermal Resistance Junction to Case information added see Table 1. on page 3. - Macromodel insertion in paragraph 5 on page 9. Changes
April 2006
2
14/15
TS274
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